The present invention relates to logic circuit simulation method for verifying a logic circuit by use of a computer and in particular to a logic circuit simulation method suitable for verifying a large scale logic circuit.
In general, the logic circuit simulation is used for verifying whether a logic circuit is properly designed. Usually, for this kind of simulation, logic verification is effected by forming an object logic circuit on a computer for general use, giving an input terminal thereof signal information such as 0, 1 etc. storing signal variation information of each gate, element, etc. within the circuit in a file such as a disc, and comparing it with an expected value. However, for the logic simulation of a large scale logic circuit, the amount of file for storing the variation information of the output of all the elements, etc. is enormous and therefore because of physical restriction it is necessary to restrict information outputted to the file. For this reason information necessary for searching the cause of erroneous operations in the simulation object logic circuit is apt to be short and heretofore a plurality of logic simulation processes have been carried out for the same logic circuit in order to search the cause of one erroneous operation.
As a known example, by which a new logic simulation is effected on the basis of results of a logic simulation, e.g. Japanese Patent Unexamined Publication 59-117660 can be cited.
According to the prior art techniques described above, it is necessary to effect a plurality of logic simulation processes for the same object logic circuit in order to search the cause of one erroneous operation. Since, for a large scale logic circuit, operations by means of a computer necessary for every logic simulation take a long time and further the amount of the logic simulation operations in order to search the cause of erroneous operations increases. Also computer operation time increases and the period of time for searching the cause is elongated.